A Meta-Interpreter for Circuit-Extraction
نویسنده
چکیده
The design of a VLSI circuit consists of a description of the circuit in terms of its components and subcomponents at various levels of detail To verify that the layout of a VLSI circuit conforms to its design one needs to work back wards from the lowest level description of the circuit and recognize the higher level components it constitutes This paper is concerned with the application of logic programming techniques in the formal veri cation of the structural cor rectness of the VLSI circuit layouts In particular we review Michael Dukes Generalized Extraction System GES that compiles design descriptions into a set of extraction rules and then study the bene ts and the limitations of using a meta interpreter approach to extrac tion
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